1. Field of the Invention
The present invention relates generally to methods of fabricating semiconductor devices having metal gate patterns, and more particularly to a method of fabricating a semiconductor that includes selective oxidation to reduce damage to the metal gate pattern caused by dry etching.
2. Description of the Related Art
Due to a continuing interest in increasing the integration density of semiconductor devices, the dimensions of various structural elements such as capacitors and gate electrodes utilized to form such semiconductor devices also tend to be reduced. Because of the increase in the integration density, materials having a low resistivity have been used to decrease signal delay. For example, metal gates which use a metallic material having a low resistivity have been utilized for lowering the sheet resistance of a gate and lowering the height of a gate stack. These studies have led to the development of metal gates incorporating a tungsten/tungsten nitride/polysilicon stack structure.
Forming a metal gate stack may include forming a gate insulating layer on a silicon substrate, sequentially stacking a polysilicon layer, a tungsten nitride layer, a tungsten layer, and a gate mask layer, forming an etch mask using a photolithographic process, and performing a dry etching process. However, the surface of the silicon substrate and the sidewalls of the metal gate pattern exposed to the dry etching process may be damaged by the dry etching process. An oxidation process (e.g., a “gate polysilicon reoxidation process”) may be performed to correct damage caused by the dry etching process. One example of a conventional gate polysilicon reoxidation process is a rapid thermal process performed in an atmosphere of a gas mixture of O2 gas and NF3 gas, such as is described in U.S. Pat. No. 5,672,525, the contents of which are incorporated by reference in their entirety.
The gate polysilicon reoxidation process may be carried out using a dry oxidation process. In a dry oxidation process, however, the exposed surface of a tungsten layer, which may be a metal layer included in the metal gate pattern, may be oxidized by the dry oxidation process. This oxidation of the tungsten layer may result in a reduction in the effective sectional area of the gate. As a result, the resistance of a gate line (e.g., a conductive line), may be increased, which may cause a delay of a signal transmission. Further, the oxidation of the tungsten layer may cause the metal gate pattern to have a poor vertical profile.
FIG. 1 is a graph illustrating the thickness of a gate oxide layer with respect to the gate length after a conventional selective oxidation was performed. Referring to FIG. 1, selective oxidation was performed on a gate pattern that included a gate oxide layer and a polysilicon layer formed on a silicon substrate. The selective oxidation was performed in a rapid thermal process (RTP) apparatus and a furnace apparatus under various process conditions. As shown in FIG. 1, when the gate length was 180 nm or more, the gate oxide layer had a thickness of about 55 Å at approximately the center of the gate pattern. When the gate length was 90 nm or less, the gate oxide layer had a thickness of from about 85 to about 150 Å. As reflected in these results, when the gate length is small, the selective oxidation process may result in a dramatic and undesirable increase in the thickness of the gate oxide layer due to a “bird's beak” effect.
Selective oxidation using a partial pressure ratio of H2O and H2 in an H2-rich wet oxidation process may oxidize a polysilicon layer and a silicon substrate and may reduce the oxidation of the metal layers included in the metal gate pattern. As reflected in Table 1, below, both the oxidation rates for silicon and polysilicon and the ratios of those rates can vary depending on the particular oxidation process employed. Table 1 provides the results obtained by measuring the thicknesses of oxide layers formed on the surfaces of a silicon substrate and a polysilicon layer, after performing both a conventional dry oxidation and selective oxidation processes, respectively.
TABLE 1Dry oxidationSelective oxidationClassification850° C., 50 Å850° C., 50 Å850° C., 30 ÅThickness T1 of oxide 63.14 Å 50.53 Å30.86 Ålayer on siliconsubstrateThickness T2 of oxide144.84 Å158.59 Å93.16 Ålayer on polysiliconlayerT2/T12.293.143.02
As shown Table 1, the silicon substrate and the polysilicon layer had an original thickness of 50 Å. Each of the silicon substrate and the polysilicon layer were oxidized by dry oxidation and selective oxidation at 850° C. When the dry oxidation was performed, the oxide layer formed on the polysilicon layer was approximately 2.2 times as thick as the oxide layer formed on the silicon substrate. By comparison, when selective oxidation was performed, the oxide formed on the polysilicon layer was approximately 3.1 times as thick as the oxide layer formed on the silicon substrate.
When the silicon substrate and the polysilicon layer had an original thickness of 30 Å and selective oxidation was performed, the oxide layer formed on the polysilicon layer was approximately 3.0 times as thick as that formed on the silicon substrate after wet selective oxidation (e.g., the oxidation rate (T2/T1) of the polysilicon layer was approximately 3.0 times as high as that of the silicon substrate.
FIG. 2A is a photograph illustrating the thickness of a gate oxide layer at the edge of a gate pattern (with no capping layer) according to a conventional selective oxidation process. FIG. 2B is a photograph illustrating the thickness of the gate oxide layer at the center of the gate pattern shown in FIG. 2A. Prior to conducting the selective oxidation process, the gate oxide layer had a thickness of approximately 55 Å. As shown in FIG. 2A, after the selective oxidation process, the gate oxide layer had a thickness of approximately 98 Å at the edge of the gate pattern and a thickness of approximately 90 Å at the center of the gate pattern. Thus, the thickness of the gate oxide layer, both at the edge of the gate pattern and at the center of the gate pattern, was increased. As a result, the gate oxide layer will have an increased likelihood of exhibiting punch-through failures.
Although conventional selective oxidation may correct damage caused by etching when a metal gate is used, dry selective oxidation fails to control the thickness of the gate oxide layer, and poses a particular problem for designs utilizing smaller gate lengths. Also, since the increased gate oxide layer is typically an oxidized polysilicon layer, the quality of the gate oxide layer may be degraded.